The present invention relates to an electrically erasable and programmable read only memory (EEPROM) device as a non-volatile semiconductor memory device and a method for manufacturing the same, and, more particularly, to an EEPROM device in which a high voltage is applied to the chip during memory cell operation and a method for the manufacturing the same.
Along with the progress of computer systems, the need for large-capacity non-volatile memories adaptable to high-speed operation, such as memory cards, has increased. Among these non-volatile memories, there has been an increased need for EEPROMs comprised of a floating gate and a control gate and which can electrically erase and program data. Therefore, a variety of cell structures for EEPROMs have been suggested for providing higher integration density, larger capacity and faster performance.
A NAND-structured memory cell has been developed in order to achieve cell area reduction without stressing the fabrication technology. An advanced NAND structured flash EEPROM has been suggested (see "A 2.3 um.sup.2 Memory Cell Structure For NAND EEPROMs" by R. Shirota et al. IEDM, 1990, pp 103-106).
FIG.1 is a sectional view illustrating the above NAND-structured EEPROM which is manufactured as follows. First, a first P-well 2 (in a cell array region) and a second P-well 3 (in a peripheral circuit region) are formed in the upper portion of an N-type semiconductor substrate 1. Then, a cell array comprised of an EEPROM is formed on first P-well 2, an NMOS transistor of the peripheral circuit is formed on a portion of second P-well 3, and an N-well 4 on which a PMOS transistor of the peripheral circuit is to be formed, is formed in a portion of second P-well 3. In order to manufacture the above EEPROM, ions are implanted three times for forming three impurity-doped regions (or bulks): one for forming first P-well 2 on which the cell array is to be formed, one for forming second P-well 3 on which the NMOS transistor of the peripheral circuit is formed, and one for forming N-well 4 on which PMOS transistor of the peripheral circuit is formed.
FIG. 2 shows a portion of an equivalent circuit diagram of an EEPROM device using the aforementioned conventional EEPROM cell and an erase and write (or program) operation. The program operation of a selected cell, is carried out by charging electrons into the floating gate and raising the cell's threshold voltage. This is accomplished by applying 0.3 V to a selected bit line BL(1) of the cell array and 7 V to an unselected bit line BL(2) of the cell array as a program preventing voltage, and applying 10 V to the unselected control gate and 18 V to the selected control gate, respectively. The 18V applied to the selected cell's control gates is coupled so that about 10 V is induced at the floating gate and 0.3 V is transferred to the selected cell's channel. Then, a nearly 10 MeV field applied between the opposite sides of a nearly 100 .ANG.-thick tunnel oxide layer which exists between the channel and floating gate, causes the floating gate electrode to be charged with electrons by the Fowler-Nordheim (F-N) tunnelling effect. Thus, a datum is written into the selected memory cell.
Conversely, the erase operation, which is carried out by discharging the electrons within the floating gate electrode to thereby lower the threshold voltage of the cell, is accomplished by applying 20 V to the P-well 2 on which the cell array is formed, opening the bit-line and source-line, and grounding the control gate. Thereby, the electrons within the floating gate are discharged by the field between the ends of the tunnel oxide layer. Here, in order to protect the transistor of the peripheral circuit which operates at +5 V (Vcc) from the approximately 20 V applied to the P-well 2 of the cell array during the erase operation, transistors are formed on another P-well 3 which is electrically isolated and independent of the P-well 2 of the cell array.
A read operation is performed according to the data determination. The data is determined by the bit-line current path fluctuating between "on" and "off" states according to the positive or negative value of the threshold voltage of the selected cells.
For manufacturing the above conventional NAND EEPROM device, a photolithography process for forming the well structures is performed twice: First, that is, for forming a first P-well 2 on which a cell array is to be formed and a second P-well 3 on which the NMOS transistor of the peripheral circuit is to be formed; Second for forming an N-well 4 which is located within the second P-well 3, on which the PMOS transistor of the peripheral circuit is to be formed on the N-type semiconductor substrate 1.
However, the conventional NAND EEPROM device as described above exhibits certain drawbacks. First, since the N-type substrate 1 is applied with a high voltage concurrently with the erase operation which applies 20 V to the P-well 2 on which the cell array exists, transistors cannot be formed directly on the N-type substrate 1. Also, since the transistors of the peripheral circuit are formed on a P-well 3 and an N-well 4 within this P-well 3, the bulk resistance is increased. Accordingly, latchup and other delitorious electrical characteristics occur.